Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
D2–D0 <TEST PATTERNS> Test Patterns to verify capture
000 Normal ADC operation
001 Outputs all zeros
010 Outputs all ones
011 Outputs toggle pattern
100 Outputs digital ramp
101 Outputs custom pattern
110 Unused
111 Unused
D3 Bit-wise/Byte-wise selection (DDR LVDS mode ONLY)
0 Bit wise – even bits(D0,D2..D12) on CLOCKOUT rising edge, odd bits(D1,D3..D13) on CLOCKOUT falling edge
1 Byte wise – lower 7 bits (D0,D1..D6) on CLOCKOUT rising edge, upper 7 bits(D7,D8..D13) on CLOCKOUT falling edge.
D4 <DATA FORMAT> Data format selection
0 2s complement
1 Straight binary
24 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42