Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
DESCRIPTION OF SERIAL REGISTERS
Table 8.
A7–A0
D7 D6 D5 D4 D3 D2 D1 D0
(hex)
<RST>
<SERIAL
00 0 0 0 0 0 0
READOUT>
Software Reset
D1 <RST>
0 Software reset applied – resets all internal registers and self-clears to 0.
D0 <SERIAL READOUT>
0 Serial readout disabled. SDOUT pin is forced low or high by the device ( and not put in high-impedance state)
1 Serial readout enabled, SDOUT functions as serial data readout pin.
Table 9.
A7–A0
D7 D6 D5 D4 D3 D2 D1 D0
(hex)
10 <CLKOUT STRENGTH> 0 0 0 0 0 0
D7–D6 <CLKOUT STRENGTH> Output clock buffer drive strength control
01 WEAKER than default drive
00 DEFAULT drive strength
11 STRONGER than default drive strength (recommended for load capacitances > 5 pF)
10 MAXIMUM drive strength (recommended for load capacitances > 5 pF)
Table 10.
A7–A0
D7 D6 D5 D4 D3 D2 D1 D0
(hex)
LVDS CURRENT> LVDS
<CURRENT DOUBLE>
11 0 0 buffer current DATAOUT STRENGTH>
LVDS buffer current double
programmability
D1–D0 <DATAOUT STRENGTH> Output data buffer drive strength control
01 WEAKER than default drive
00 DEFAULT drive strength
11 STRONGER than default drive strength (recommended for load capacitances > 5 pF)
10 MAXIMUM drive strength (recommended for load capacitances > 5 pF)
D3–D2 <LVDS CURRENT> LVDS Current programmability
00 3.5 mA
01 2.5 mA
10 4.5 mA
11 1.75 mA
D5–D4 CURRENT DOUBLE> LVDS Current double control
00 Default current, set by <LVDS CURR>
01 LVDS clock buffer current is doubled, 2x <LVDS CURR>
10 LVDS data and clock buffers current are doubled, 2x <LVDS CURR>
11 Unused
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42