Datasheet

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R EGISTER A DDR ESS (A7:A0) = 0x00 REGISTER DAT A (D7:D 0) = 0x01
SDA TA
SC LK
SEN
A) Enable serial read back (<SERIAL READOUT> = 1)
(Serial register writes are disabled)
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0SDA TA
SC LK
SEN
SDOUT
B) Read contents of register 0x14.
This register has been initialized with 0xB0
(over-ride bit set, LVDS interface, 3.5dB coarse gain, internal reference, normal operation)
REGISTER ADD RESS (A 7:A0) = 0x14 R EGIST ER D ATA (D7:D0) = XX (don’ t care)
SDOUT
1 0 1 1 0 0 0 0
Pin SD OUT is NOT in high-im pedance state; it is f orced low or hig h by the de vice ( <SERIA L REA DOUT> = 0)
Pin SDOUT func tio ns as serial readou t (<SERIA L REA DOUT> = 1)
ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
Figure 7. Serial Readout
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range T
MIN
= –40°C to T
MAX
= 85°C, unless otherwise
noted.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Delay from power-up of AVDD and DRVDD to RESET pulse
t
1
Power-on delay 5 ms
active
t
2
Reset pulse width Pulse width of active RESET signal 10 ns
t
3
Register write delay Delay from RESET disable to SEN active 25 ns
t
PO
Power-up time Delay from power-up of AVDD and DRVDD to output stable 7 ms
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42