Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16
th
SCLK falling edge
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be
loaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits the register data. The interface can work with
SCLK frequency from 20 MHz down to low speeds (few Hertz), and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to their default values. This can be done in one of two
ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as
shown in Figure 6.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit to high. This initializes internal
registers to their default values and then self-resets the <RST> bit to low. In this case the RESET pin is kept
low.
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range T
MIN
= –40°C to T
MAX
= 85°C, AVDD = 3.3 V,
DRVDD = 1.8 V to 3.3 V, unless otherwise noted.
PARAMETER MIN TYP MAX UNIT
f
SCLK
SCLK frequency > DC 20 MHz
t
SLOADS
SEN to SCLK setup time 25 ns
t
SLOADH
SCLK to SEN hold time 25 ns
t
DS
SDATA setup time 25 ns
t
DH
SDATA hold time 25 ns
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