Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is
shown in Figure 5.
Table 4. SCLK (Analog Control Pin)
VOLTAGE APPLIED ON SCLK DESCRIPTION
0 0dB gain and Internal reference
+200mV/-0mV
(3/8)AVDD 0dB gain and External reference
+/- 200mV
(5/8)2AVDD 3.5dB Coarse gain and External reference
+/- 200mV
AVDD 3.5dB Coarse gain and Internal reference
+0mV/-200mV
Table 5. SEN (Analog Control Pin)
VOLTAGE APPLIED ON SEN DESCRIPTION
0 2s complement format and DDR LVDS output
+200mV/-0mV
(3/8)AVDD Straight binary and DDR LVDS output
+/- 200mV
(5/8)AVDD Straight binary and parallel CMOS output
+/- 200mV
AVDD 2s complement format and parallel CMOS output
+0mV/-200mV
Table 6. CTRL1, CTRL2 and CTRL3 (Digital Control Pins)
CTRL1 CTRL2 CTRL3 DESCRIPTION
LOW LOW LOW Normal operation
LOW LOW HIGH Channel A output buffer disabled
LOW HIGH LOW Channel B output buffer disabled
LOW HIGH HIGH Channel A and B output buffer disabled
HIGH LOW LOW Power down global
HIGH LOW HIGH Channel A standby
HIGH HIGH LOW Channel B standby
MUX mode of operation (only with CMOS interface Channel A and B data is multiplexed and
HIGH HIGH HIGH
output on DB13 to DB0 pins. See Multiplexed output mode for detailed description.
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