Datasheet

ADS62P45, ADS62P44

ADS62P43, ADS62P42

www.ti.com

SLAS561C –JULY 2007– REVISED FEBRUARY 2012

DEVICE CONFIGURATION

ADS62P4X can be configured independently using either parallel interface control or serial interface

programming.

USING PARALLEL INTERFACE CONTROL ONLY

To control the device using the parallel interface, keep RESET tied to high (AVDD). Pins SEN, SCLK, CTRL1,

CTRL2 and CTRL3 can be used to directly control certain modes of the ADC. After power-up, the device will

automatically get configured as per the parallel pin voltage settings (Table 4 to Table 6).

In this mode, SEN and SCLK function as parallel analog control pins, which can be configured using a simple

resistor divider (Figure 5, using resistors <= 10% tolerance ). Table 3 has a brief description of the modes

controlled by the parallel pins. SDATA has no parallel function and can be kept low.

Table 3. Parallel Pin Definition

PIN TYPE OF PIN CONTROLS MODES

SCLK Analog control pins Coarse Gain and internal/external reference

(controlled by analog

SEN LVDS/CMOS interface and output data format

voltage levels, see )

CTRL1

Digital control pins

CTRL2 (controlled by digital Together control various powerdown modes and MUX mode.

logic levels)

CTRL3

USING SERIAL INTERFACE PROGRAMMING ONLY

To program the device using the serial interface, keep RESET low. Pins SEN, SDATA, and SCLK function as

serial interface digital pins and are used to access the internal registers of ADC. The registers must first be reset

to their default values either by applying a pulse on RESET pin or by setting bit <RST> = 1. After reset, the

RESET pin must be kept low.

The serial interface section describes the register programming and register reset in more detail. Since the

parallel pins (CTRL1, CTRL2, CTRL3) are not used in this mode, they must be tied to ground.

USING BOTH SERIAL INTERFACE and PARALLEL CONTROLS

For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)

can also be used to configure the device. To allow this, keep RESET low.

The parallel interface control pins CTRL1 to CTRL3 are available. After power-up, the device will automatically

get configured as per the voltage settings on these pins (Table 6).

SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of

ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by

setting bit <RST> = 1. After reset, the RESET pin must be kept low. The serial interface section describes the

Since the power down modes can be controlled using both the parallel pins and serial registers, the priority

between the two is determined by <OVRD> bit. When <OVRD> bit = 0, pins CTRL1 to CTRL3 control the power

down modes. With <OVRD> = 1, register bits <POWER DOWN> control these modes, over-riding the pin

settings.

Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42