Datasheet

E E E E E EE E
OO O O O O O O OO
Input
Clock
CLKOUTM
CLKOUTP
Output Data
DXP, DXM
DDR
LVDS
N–10
N–9
N–1
N
N+1 N+2
N–9N–10 N N+2
CLKOUT
Output Data
D0–D13
Parallel
CMOS
Input
Signal
Sample
N
N+1
N+2
N+3
N+4
t
h
t
PDI
t
a
t
su
t
h
t
PDI
CLKM
CLKP
N+14
N+15
N+16
t
su
E – Even Bits D0,D2,D4,D6,D8,D10,D12
O – Odd Bits D1,D3,D5,D7,D9,D11,D13
N+1N–1
14 Clock Cycles
(1)
14 Clock Cycles
(1)
EE E E E E E E E E
T0106-04
Input
Clock
Output
Clock
Output
DataPair
CLKM
CLKOUTM
Dn_Dn+1_P,
Dn_Dn+1_M
CLKP
t
PDI
t
h
t
h
t
su
t
su
CLKOUTP
(1)
Dn – BitsD0,D2,D4,D6,D8,D10,D12
(2)
Dn+1 – BitsD1,D3,D5,D7,D9,D11,D13
Dn
(1)
Dn+1
(2)
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C –JULY 2007– REVISED FEBRUARY 2012
(1) Latency is 10 clock cycles in low-latency mode.
Figure 1. Latency
Figure 2. LVDS Mode Timing
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42