Datasheet

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561C –JULY 2007– REVISED FEBRUARY 2012 www.ti.com
Table 2. Timing Characteristics at Lower Sampling Frequencies
Sampling
t
PDI
CLOCK PROPAGATION DELAY,
frequency, t
su
DATA SETUP TIME, ns t
h
DATA HOLD TIME, ns
ns
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS INTERFACE, DRVDD = 2.5 V TO 3.6 V
40 10.5 12 10.3 11.8
5.8 7.3 8.8
20 23 24.5 23 24.5
LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V
40 8.5 10 1 2.3
3.5 5.5 7.5
20 21 22.5 1 2.3
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