ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Check for Samples: ADS62P45, ADS62P44, ADS62P43, ADS62P42 FEATURES 1 • • • • • • • • • • • Maximum Sample Rate: 125 MSPS 14-Bit Resolution with No Missing Codes 95 dB Crosstalk Parallel CMOS and DDR LVDS Output Options 3.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. DRGND DRVDD AGND AVDD ESD damage can range from subtle performance degradation to complete device failure.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage (1) DRVDD Output buffer supply voltage CMOS interface 3 3.3 3.6 V 1.65 1.8 to 3.3 3.6 V 3 3.3 3.6 V LVDS interface ANALOG INPUTS Differential input voltage range VIC 2 Vpp 1.5 ± 0.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 v to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1) (continued) Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF(2), IO = 3.5 mA, RL = 100 Ω(3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 2. Timing Characteristics at Lower Sampling Frequencies Sampling frequency, MSPS tsu DATA SETUP TIME, ns MIN TYP MAX tPDI CLOCK PROPAGATION DELAY, ns th DATA HOLD TIME, ns MIN TYP MAX MIN TYP MAX 5.8 7.3 8.8 3.5 5.5 7.5 CMOS INTERFACE, DRVDD = 2.5 V TO 3.6 V 40 10.5 12 10.3 11.8 20 23 24.5 23 24.5 LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V 10 40 8.5 10 1 2.3 20 21 22.5 1 2.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com CLKM Input Clock clock CLKP t PDI PDI Output Clock clock CLKOUTCLKOUT t su su Output Data data DAn, DBn t hh Dn * Dn CLKM Input Clock clock CLKP t START PDI t DV su Output Data data DAn, DBn Dn * Dn *Dn - Bits D0, D1, D2, . . . of Channels A & B Figure 3.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DEVICE CONFIGURATION ADS62P4X can be configured independently using either parallel interface control or serial interface programming. USING PARALLEL INTERFACE CONTROL ONLY To control the device using the parallel interface, keep RESET tied to high (AVDD). Pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain modes of the ADC.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DETAILS OF PARALLEL CONFIGURATION ONLY The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is shown in Figure 5. Table 4. SCLK (Analog Control Pin) VOLTAGE APPLIED ON SCLK DESCRIPTION 0 +200mV/-0mV 0dB gain and Internal reference (3/8)AVDD +/- 200mV 0dB gain and External reference (5/8)2AVDD +/- 200mV 3.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com AVDD (5/8) AVDD 3R (5/8) AVDD GND AVDD 2R (3/8) AVDD (3/8) AVDD 3R To Parallel Pin GND S0321-01 Figure 5.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com SERIAL INTERFACE The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low).
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Register Address SDATA A7 A6 A5 A4 A3 A2 Register Data A1 A0 D7 D6 t(SCLK) D5 D4 D3 D2 D1 D0 t(DH) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-01 Figure 6. Serial Interface Timing Serial Register Readout (only when CMOS interface is used) The device includes an option where the contents of the internal registers can be read back.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com A) Enable serial read back ( = 1) (Serial register writes are disabled) R EGIST ER A DDR ESS (A7:A0) = 0x00 SDA TA 0 0 0 0 0 0 0 REGISTER DAT A (D7:D 0) = 0x01 0 0 0 0 0 0 0 0 1 SC LK SEN SDOUT Pin SD OU T is NOT in hig h-im ped ance state; it is forced low o r h ig h b y th e de vice ( = 0) B) Read contents of register 0x14.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Power Supply AVDD, DRVDD t1 RESET t2 t3 SEN T0108-01 NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 8.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com SERIAL REGISTER MAP Table 7.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DESCRIPTION OF SERIAL REGISTERS Table 8. A7–A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0 00 0 0 0 0 0 0 Software Reset D1 0 Software reset applied – resets all internal registers and self-clears to 0. D0 0 1 Serial readout disabled.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 11.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 13. A7–A0 (hex) D7 D6 D5 D4 D3 14 Over-ride bit 0
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com D2–D0 000 001 010 011 100 101 110 111 Test Patterns to verify capture Normal ADC operation Outputs all zeros Outputs all ones Outputs toggle pattern Outputs digital ramp Outputs custom pattern Unused Unused D3 0 1 Bit-wise/Byte-wise selection (DDR LVDS mode ONLY) Bit wise – even bits(D0,D2..D12) on CLOCKOUT rising edge, odd bits(D1,D3..
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 15. A7–A0 (hex) D7 D6 D5 D4 17 0 0 0 0 D2–D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Others D3 D2 D1 D0 0 to 6 dB gain in 0.5 dB steps Gain programmability in 0.5 dB steps 0 dB gain, default after reset 0.5 dB gain 1.0 dB gain 1.5 dB gain 2.0 dB gain 2.5 dB gain 3.0 dB gain 3.5 dB gain 4.0 dB gain 4.5 dB gain 5.0 dB gain 5.5 dB gain 6.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 17. A7–A0 (hex) D7 1A D6 D5 D4 D3 D2 Offset correction time constant D1 D0 0 to 0.5 dB, steps of 0.05 dB D2–D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels) 0 dB gain, default after reset +0.5 dB gain +0.10 dB gain +0.15 dB gain +0.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (CMOS INTERFACE) PIN NAME DESCRIPTION AVDD Analog power supply AGND Analog ground CLKP, CLKM INM_A, INP_A PIN NUMBER NUMBER OF PINS 16, 33, 34 3 17, 18, 21, 22, 24, 27, 28, 31, 32 9 Differential input clock 25, 26 2 Differential input signal-Channel A. When not used, the analog input pins (INM_A, INP_A) MUST be tied to VCM and CANNOT be floated.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (LVDS INTERFACE) (continued) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS RESET Serial interface RESET input. In serial interface mode, the user must initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset (refer to Serial Interface section). In parallel interface mode, the user has to tie RESET pin permanently high.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Pin Assignments (LVDS INTERFACE) (continued) PIN NAME DESCRIPTION PIN NUMBER NUMBER OF PINS DRVDD Digital supply 1, 38, 48, 58 4 DRGND Digital ground 39, 49, 59, 64 and PAD 4 PAD Digital ground. Solder the bottom pad to the digital ground on the board using multiple vias for good electrical and thermal performance.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 88.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 88.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL 0 0 SFDR = 88.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS – LOW SAMPLING FREQUENCIES All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS – LOW SAMPLING FREQUENCIES (continued) All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) DRVDD current (CMOS) vs SAMPLING FREQUENCY across load capacitance at 2 MHz input frequency 60 3.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION ADS62P4X is a low power 14-bit dual channel pipeline ADC family fabricated in a CMOS process using switched capacitor techniques. The conversion process is initiated by a rising edge of the external input clock.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com 1 0 Magnitude − dB −1 −2 −3 −4 −5 −6 −7 0 100 200 300 400 500 fI − Input Frequency − MHz 600 G080 Figure 83. ADC Analog Bandwidth Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com 9 C − Capacitance − pF 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 f − Frequency − MHz 600 G082 Figure 85. ADC Analog Input Capacitance (Cin) Across Frequency Using RF-Transformer Based Drive Circuits Figure 86 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that can be used for low input frequencies (about 100 MHz).
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com ADS62P4x 0.1 mF INP 50 W 0.1 mF 50 W 50 W 50 W INM 1:1 1:1 VCM S0164-05 Figure 87. Drive Circuit at High Input Frequencies Using Differential Amplifier Drive Circuits Figure 88 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interface to the ADC analog input pins.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Input Common-Mode To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-μF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 165 μA (at 125 MSPS). Equation 1 describes the dependency of the common-mode current and the sampling frequency.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com COARSE GAIN AND PROGRAMMABLE FINE GAIN ADS62P4X includes gain settings that can be used to get improved SFDR performance (over 0dB gain mode). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 20. The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The fine gain is programmable in 0.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Clock Buffer Lpkg » 2 nH 10 W CLKP Cbond » 1 pF Ceq Ceq 5 kW Resr » 100 W VCM 6 pF 5 kW Lpkg » 2 nH 10 W CLKM Cbond » 1 pF Resr » 100 W Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer S0275-02 Figure 90. Internal Clock Buffer 100k Impedance − Ω 10k 1k 100 10 5 25 45 65 85 105 fS − Sampling Frequency − MSPS 125 G083 Figure 91.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS62P4x S0167-06 Figure 92. Differential Clock Driving Circuit Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 93. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM ADS62P4x S0168-10 Figure 93.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com POWER DOWN ADS62P4X has three powerdown modes – power down global, individual channel standby and individual channel output buffer disable. These can be set using either the serial register bits or using the control pins CTRL1 to CTRL3. Table 21.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DIGITAL OUTPUT INFORMATION ADS62P4X provides 14-bit data per channel and a common output clock synchronized with the data. The output interface can be either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com CMOS Mode Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com CLKOUTM CLKOUTP DA0 (DB0) D0 D1 D0 D1 DA2 (DB2) D2 D3 D2 D3 DA4 (DB4) D4 D5 D4 D5 DA6 (DB6) D6 D7 D6 D7 DA8 (DB8) D8 D9 D8 D9 DA10 (DB10) D10 D11 D10 D11 DA12 (DB12) D12 D13 D12 D13 Sample N Sample N+1 T0110-02 Figure 96. DDR LVDS Interface LVDS Buffer Current Programmability The default LVDS buffer output current is 3.5 mA.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Figure 97. LVDS Eye Diagram – No Internal Termination, External Termination = 100 Ω Figure 98.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Output Data Format Two output data formats are supported – 2s complement and straight binary. They can be selected using the serial interface register bit or controlling the SEN pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DETAILS OF DIGITAL PROCESSING BLOCK CLIPPER From ADC Output 14 Bits 14 Bits 14 Bits 14 Bits 14 Bits To output buffers LVDS or CMOS Fine Gain (0 to 6 dB 0.05 dB Steps) 24 TAP FILTER - LOW PASS - HIGH PASS - BAND PASS Gain Correction (0.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com It is also possible to freeze the offset correction using the serial interface (). Once frozen, the offset estimation becomes inactive and the last estimated value is used for correction every clock cycle. Note that the offset correction is disabled by default after reset. Figure 101 shows the time response of the offset correction algorithm, after it is enabled.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Decimation Filters ADS62P4X includes option to decimate the ADC output data with in-built low pass, high pass or band pass filters. The decimation rate and type of filter can be selected using register bits ( DECIMATION RATE) and ( DECIMATION FILTER TYPE). Decimation rates of 2, 4, or 8 are available and either low pass, high pass or band pass filters can be selected (see Table 24).
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com 5 0 Magnitude − dB −5 −10 Low Pass High Pass −15 −20 −25 −30 −35 −40 −45 0.0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency − f/fS G085 Figure 102. Decimate by 2 Filter Response 5 0 Magnitude − dB −5 −10 Low Pass High Pass −15 −20 −25 −30 −35 −40 −45 0.0 0.1 0.2 0.3 0.4 Normalized Frequency − f/fS 0.5 G086 Figure 103.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Table 25. Predefined Coefficients for Decimation by 2 Filters COEFFICIENTS DECIMATE BY 2 LOW-PASS FILTER HIGH-PASS FILTER h0 23 -22 h1 -37 -65 h2 -6 -52 h3 68 30 h4 -36 66 h5 -61 -35 h6 35 -107 h7 118 38 h8 -100 202 h9 -197 -41 h10 273 -644 h11 943 1061 Table 26.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Custom Filter Coefficients without Decimation The filter with custom coefficients can also be used with the decimation mode disabled. In this mode, the filter implementation is 12-tap FIR: y(n) + ǒ21 Ǔx[h6 11 x(n) ) h7 x(n * 1) ) h8 x(n * 2) ) AAA ) h11 x(n * 5) ) h11 x(n * 6) ) AAA ) h7 x(n * 10) ) h6 x(n * 11)] (5) Table 27.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide (SLAU237) for details on layout and grounding. Supply Decoupling As the ADS62P4X already includes internal decoupling, minimal external decoupling can be used without loss in performance.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay will be different across channels.
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). P THD + 10Log 10 s PN (9) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).
ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561C – JULY 2007 – REVISED FEBRUARY 2012 www.ti.com REVISION HISTORY Changes from Revision A (February 2008) to Revision B Page • Added Aperature delay matching to TIMING REQUIREMENTS — LVDS AND CMOS MODES ........................................ 8 • Added tSTART description to TIMING REQUIREMENTS — LVDS AND CMOS MODES ..................................................... 9 • Added tDV description to TIMING REQUIREMENTS — LVDS AND CMOS MODES ...............
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS62P42IRGCR VQFN RGC 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS62P42IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS62P43IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS62P42IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS62P42IRGCT VQFN RGC 64 250 336.6 336.6 28.6 ADS62P43IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS62P43IRGCT VQFN RGC 64 250 336.6 336.6 28.6 ADS62P44IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS62P44IRGCT VQFN RGC 64 250 336.6 336.6 28.
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