Datasheet

4.1.3 Test Result With Onboard VCXO and Differential LVPECL Clock
4.2 TSW1100
Connecting to FPGA Platforms www.ti.com
For the same setup as explained in the previous section, when Clock Option 3 (Table 7 ) was used, the
FFT was captured as shown in Figure 12 . The test results with Clock Option 2 are better than with Clock
Option 3. That is why Option 2 (clock with crystal filter) is recommended over the differential LVPECL
output.
Figure 12. ADC Performance With Clock Through Onboard VCXO,
CDCE72010 Configured for Differential LVPECL Output
When the ADS62PXX is configured in CMOS output mode users can use TI's TSW1100 capture board.
Several additional board configuration steps are required before using this option.
• Remove resistor packs with the following reference designators: RN7, RN8, RN9, RN10, RN11, RN12,
RN13 and RN14.
• Install TI's SN74AVC16244 buffer into U12 and U13.
• If using the parallel interface mode (JP11=1-2), configure the ADC in CMOS output mode using the
silkscreen on JP14.
ADS62PXXEVM 24 SLAU237A – May 2008 – Revised April 2009
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