ADS62xxEVM User's Guide User's Guide Literature Number: SLAU197B April 2007 – Revised July 2009
SLAU197B – April 2007 – Revised July 2009 Submit Documentation Feedback
Contents 1 Overview ............................................................................................................................. 5 1.1 2 3 4 ADS62xxEVM Quick-Start Procedure .................................................................................. 5 Circuit Description ............................................................................................................... 7 2.1 Schematic Diagram .........................................................................
www.ti.com List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SFDR vs Frequency Using a Single Transformer ....................................................................... 8 SFDR vs Frequency Using a Dual Transformer ......................................................................... 8 ADS62xxEVM Setup ....................................................................................................... 12 Layer 1, Top Layer .....................................................................
User's Guide SLAU197B – April 2007 – Revised July 2009 1 Overview This user's guide gives a general overview of the evaluation module (EVM) and provides a general description of the features and functions to be considered while using this module. This manual is applicable to the ADS6245, ADS6244, ADS6243, ADS6225, ADS6224, and ADS6223, which collectively are referred to as ADS62xx.
Overview www.ti.com 7. ADS62xx: Using a low-phase-noise, filtered frequency generator with 50-Ω source output impedance, generate a 0-V offset, 1.5-Vrms sine-wave clock into J12. The frequency of the clock must be within the specification for the device speed grade. TI uses an Agilent 8644B with a crystal MCF filter as a clock source. 8. TSW1200: Depress SW4 (FPGA reset). This resets the logic inside the FPGA and must be done every time one changes the ADC clock frequency. 9.
www.ti.com 2 Circuit Description 2.1 Schematic Diagram Circuit Description The schematic diagram for the EVM is in Section 4.3. 2.2 ADC Circuit Function The following sections describe the function of individual circuits. Refer to the relevant data sheet for device operating characteristics. 2.2.1 ADC Operational Mode By default, the ADC is configured to operate in parallel-mode operation, because the surface-mount jumper asserts a 3.3-V state to the ADC reset pin.
Circuit Description www.ti.com For an ac-coupled system, users must use the voltage divider R9 and R18 to set the common-mode input of the amplifier, which must be set to the midpoint of the amplifier supply. C46 and C47 ac-couple the system, and the ADC inputs can then be biased by the R14 and R15 combination. Another ac-coupled approach, not supported on this EVM, would be to use a transformer at the outputs of the THS4509.
Circuit Description www.ti.com 2.2.4 ADC Clock Input Users must connect a filtered, low-phase-noise clock input to J12. A transformer, T5, provides the conversion from a single-ended clock signal into a differential clock signal. When selecting the clock signal level, users must account for the transformer having an impedance ratio of 4, with a voltage step-up of 2. 2.2.5 ADC Digital Outputs The ADS62xx ADC outputs serialized data, a bit clock (DCLK), and a frame clock (FCLK).
ADC Evaluation 3 www.ti.com ADC Evaluation This section describes how to set up a typical ADC evaluation system that is similar to what TI uses to perform testing for data sheet generation. Consequently, the information in this section is generic in nature and is applicable to all high-speed, high-resolution ADC evaluations. This section covers signal tone analysis, which yields ADC data sheet figures of merit such as signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). 3.
ADC Evaluation www.ti.com 3.2 Coherent Input Frequency Selection Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fourier transform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that the signal must be continuous-time; however, this is not practical when looking at a finite set of ADC samples, usually collected from a logic analyzer.
ADC Evaluation www.ti.com Figure 3.
Physical Description www.ti.com 4 Physical Description This section describes the physical characteristics and PCB layout of the EVM. 4.1 PCB Layout To be filled in, consult factory for details. K001 Figure 4.
Physical Description www.ti.com K002 Figure 5.
Physical Description www.ti.com K003 Figure 6.
Physical Description www.ti.com K004 Figure 7.
Physical Description www.ti.com K005 Figure 8.
Physical Description www.ti.com K006 Figure 9.
Physical Description www.ti.com 4.2 Bill of Materials Table 3 is the bill of materials for the ADS62xxEVM. Table 3. ADS62xxEVM Bill of Materials Reference Quantity Not Installed Part Footprint Part Number Manufacturer C1, C5, C8, C10 4 22 µF smd_cap_1210_p ECS-T1CC226R ol Panasonic C2, C9 2 10 µF smd_cap_1210_p ECS-H1CC106R ol Panasonic C3, C6 2 1 µF 603 ECJ-1VB1A105K Panasonic C4, C7, C22, C23, C24, C25, C26, C27, C28, C29 10 0.
Physical Description www.ti.com Table 3.
1 1 1 1 1 1 1 Banana jack black P4 Banana jack red P3 R2 750 D2 GREEN PWR_IN2 R1 750 D1 GREEN PWR_IN1 Banana jack black P2 Banana jack red 1 1 1 2 2 1 1 2 2 1 2 1 2 + + L1 2 L2 2 C10 22uF Bead 220 ohm 1 C5 22uF Bead 220 ohm 1 1 2 1 2 + + C8 22uF C1 22uF 1 2 1 2 + + C9 10uF C2 10uF 1 2 1 2 C6 1uF C3 1uF +3.3VD 1 +3.3VA 2 1 2 C7 .1uF C4 .
FPGA_RST +3.3VD 1 .1uF C16 100 R39 2 CFG1 SW1 TP6 .1uF C17 J7 J20 3 2 1 C18 .1uF 8 6 4 2 R41 10K SERIAL 1 .1uF C19 C20 .1uF 2 .1uF C21 +3.3VD 2000pF C11 R81 1K R32 1K AMP_VCM PARALLEL R33 10K +3.3VD +3.3VA 7 5 3 1 1 2 1 2 1 2 1 2 1 2 R82 1K 1/10W 5% R86 0 ohm INA_M INA_P CM CAP RESET +3.3VA TP2 TP11 TP5 CFG2 TP12 R45 1 2 3 4 5 6 7 8 9 10 11 12 49 7 5 3 1 8 6 4 2 10 .
EN D J10 S MA J11 EN D S MA SMA 4 3 2 5 4 3 2 5 SLAU197B – April 2007 – Revised July 2009 Submit Documentation Feedback 1 1 SIGNAL_INB SIGNAL_INA 1 2 1 1 1 C27 S MA .1uF 2 1 6 T3 2 EN D 6 1 1 2 3 5 4 T5 1:2 TC4-1W 49.9 R57 49.9 3 2 1 2 .1uF C28 T4 1:1 R53 1:1 WBC1-1TLB 1:1 3 1 2 3 WBC1-1TLB 5 4 49.9 R50 49.9 R47 T2 WBC1-1TLB 1:1 3 4 1 2 WBC1-1TLB T1 5 6 SMA J12 2 .1uF C24 .
AMP_VCM J2 AMP EN D 1 .1uF 16V C48 C39 .1uF 16V NC VINVIN+ CM1 PAD PD VOUT+ VOUTCM2 C36 .1uF 16V C44 .22uF R21 49.9 C41 .1uF 16V C40 10uF 10V 348 R22 R17 1 2 11 4 17 THS4509 U2 69.8 R18 499 R9 499 100 AMP_VCM 100 R12 R16 69.8 R13 12 3 10 9 C34 10uF 10V C43 .1uF 16V C42 10uF 10V PD C37 10uF 10V +5V_AMP C38 .1uF 16V 2 1 2 348 R8 5 6 7 8 S MA 4 3 2 5 C35 .1uF 16V 16 15 14 13 VSVSVSVSVS+ VS+ VS+ VS+ 1 2 1 2 24 1 -5V_AMP 49.9 R19 49.9 R10 JP6 2 3 1 C45 18pF .
SLAU197B – April 2007 – Revised July 2009 Submit Documentation Feedback FD2 SMT FIDUCIAL FD1 SMT FIDUCIAL SMT FIDUCIAL FD3 DB1_M DB1_P DB0_M DB0_P FCLK_M FCLK_P DCLK_M DCLK_P DA1_M DA1_P DA0_M DA0_P G1 G3 G5 G7 G2 G4 G6 G8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 J15 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112
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