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7. ADS62xx: Using a low-phase-noise, filtered frequency generator with 50- Ω source output impedance,
generate a 0-V offset, 1.5-Vrms sine-wave clock into J12. The frequency of the clock must be within
the specification for the device speed grade. TI uses an Agilent 8644B with a crystal MCF filter as a
clock source.
8. TSW1200: Depress SW4 (FPGA reset). This resets the logic inside the FPGA and must be done every
time one changes the ADC clock frequency.
9. ADS62xx: Using a low-phase-noise, filtered frequency generator with a 50- Ω source output impedance,
generate a 10-MHz, 0-V offset, –1-dBFS-amplitude sine-wave signal into either J10 (input channel A)
or J11 (input channel B). This provides a transformer-coupled differential input signal to the ADC. TI
uses an Agilent 8644B with an LC filter as a signal source.
10. TSW1200: Connect the TSW1200 or suitable logic analyzer to J5 to capture the resulting digital data.
If you connect a TSW1200 to capture data, follow the additional alphabetically labeled steps.
a. After installing the TSW1200 software and connecting the TSW1200 to the USB port, open the
TSW1200 software.
b. Depending on the ADC under evaluation, select from the TI ADC Section pulldown .
c. Change the ADC Sample Rate and ADC Input Frequency to match those of the signal generator.
d. After selecting a Single Tone FFT test, press the Capture Data button.
Note: Any time the clock frequency of the ADC changes during the ADC evaluation, one must reset
the FPGA deserializer by depressing SW4. This allows the deserializer to re-align the ADC
data capture to the new output clock frequency.
6 SLAU197B – April 2007 – Revised July 2009
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