Datasheet

ICLKP
ICLKM
RESET CAP
SCLK SDATA PDNA PDNB
+3.3VA
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VA
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
+3.3VD
INA_M INA_P
INB_M
INB_P
ICLKP
ICLKM
CM
DA1_P
DA1_M
DB0_P
DB0_M
DCLK_M
DCLK_P
FCLK_M
FCLK_P
CFG4
CFG3
CFG2
CFG1
FPGA_SDATA
FPGA_SCLK
SEN
FPGA_RST
FPGA_PDNA
FPGA_PDNB
DB1_P
DB1_M
DA0_P
DA0_M
SEN
FPGA_SEN
CFG2
CFG3
CFG4
CFG1
AMP_VCM
SERIAL PARALLEL
J19J19
2 4 6 8
1 3 5 7
R35 100R35 100
1
2
R72
10K
R72
10K
12
R32
1K
R32
1K
12
TP7TP7
R85
1K
R85
1K
12
TP10TP10
R42 100R42 100
1
2
C11 2000pF C11 2000pF
1
2
R45
10
R45
10
R44
10K
R44
10K
12
J18J18
2 4 6 8
1 3 5 7
R77
1K
R77
1K
12
R36
1K
R36
1K
12
TP3TP3
TP8TP8
R30
0OHM
R30
0OHM
J16J16
1 2 3
U1
ADS624X
U1
ADS624X
LGND
1
LVDD
2
CAP
3
RESET
4
LVDD
5
AGND
6
AVDD
7
AGND
8
AGND
9
INA_M
10
INA_P
11
AGND
12
AVDD
13
NC
14
CFG4
15
CM
16
AGND
17
CLKP
18
CLKM
19
AGND
20
CFG3
21
CFG2
22
CFG1
23
AVDD
24
AGND
25
INB_P
26
INB_M
27
AGND
28
AGND
29
PDNB
30
PDNA
31
SEN
32
SDATA
33
SCLK
34
LGND
35
LVDD
36
DB1_P
37
DB1_M
38
DB0_P
39
DB0_M
40
FCLK_P
41
FCLK_M
42
DCLK_P
43
DCLK_M
44
DA1_P
45
DA1_M
46
DA0_P
47
DA0_M
48
PWRPAD
49
J6J6
1 2 3
R43 100R43 100
1
2
R40
10K
R40
10K
12
C19
.1uF
C19
.1uF
12
R75
1K
R75
1K
12
R81
1K
R81
1K
12
R78
1K
R78
1K
12
R73
100
R73
100
1 2
TP5TP5
J7J7
1 2 3
TP9TP9
J9J9
1 2 3
SW1SW1
C21
.1uF
C21
.1uF
12
R86
0ohm
5%
1/10W
R86
0ohm
5%
1/10W
C20
.1uF
C20
.1uF
12
J17J17
2 4 6 8
1 3 5 7
TP11TP11
TP4TP4
R76
1K
R76
1K
12
R79
1K
R79
1K
12
J21J21
2 4 6 8
1 3 5 7
R28
1K
R28
1K
12
R74
100
R74
100
12
R38 100R38 100
1
2
R34
10K
R34
10K
12
TP12TP12
R37
100
R37
100
1
2
R39
100
R39
100
1
2
R80
1K
R80
1K
12
C18
.1uF
C18
.1uF
12
J8J8
1 2 3
R83
1K
R83
1K
12
C17
.1uF
C17
.1uF
12
R33
10K
R33
10K
12
C16
.1uF
C16
.1uF
12
C12
.1uF
C12
.1uF
12
TP6TP6
TP2TP2
R31
100
R31
100
1
2
J5J5
1 2 3
TP1TP1
R84
1K
R84
1K
12
R29
1K
R29
1K
12
R41
10K
R41
10K
12
J20J20
2 4 6 8
1 3 5 7
R82
1K
R82
1K
12
S002
Physical Description www.ti.com
Figure 11. Sheet 2 of 5
22 SLAU197B – April 2007 – Revised July 2009
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