Datasheet

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CLKOUTP
D0_D1_P,
D0_D1_M
D2_D3_P,
D2_D3_M
D4_D5_P,
D4_D5_M
D6_D7_P,
D6_D7_M
D8_D9_P,
D8_D9_M
D10_D11_P,
D10_D11_M
D12_D13_P,
D12_D13_M
D0
D2
D4
D6
D8
D10
D12
SampleN+1SampleN
D0
D2
D4
D6
D8
D10
D12
D1
D3
D5
D7
D9
D11
D13
D1
D3
D5
D7
D9
D11
D13
CLKOUTM
ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the rising edge of CLKOUTP and the odd data
bits D1, D3, D5, D7, D9, D11, and D13 are output at the falling edge of CLKOUTP. Both the rising and falling
edges of CLKOUTP must be used to capture all 14 data bits (see Figure 106 ).
Figure 106. DDR LVDS Interface
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are – 300 Ω , 185 Ω , and 150 Ω (nominal with
± 20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 65 Ω .
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100- Ω internal and 100- Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 107 and Figure 108 compare the LVDS eye diagrams without and with internal termination (100 Ω ).
With internal termination, the eye looks clean even with 10-pF load capacitance (from each output pin to ground).
The termination is programmed using register bits <DATA TERM> and <CLKOUT TERM> (see Table 11 ).
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Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142