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COMMON PLOTS
f − Frequency − MHz
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 50 100 150 200 250 300
CMRR − dBc
G077
f
S
− Sampling Frequency − MSPS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 25 50 75 100 125
P
D
− Power Dissipation − W
G078
LVDS
CMOS
f
IN
= 2.5 MHz
C
L
= 5 pF
f
S
− Sampling Frequency − MSPS
0
5
10
15
20
25
30
0 25 50 75 100 125
DRV
DD
Current − mA
G079
1.8 V, 5 pF
3.3 V, 5 pF
3.3 V, 10 pF
1.8 V, No Load
3.3 V, No Load
ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
All plots are at 25 ° C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 V
PP
differential clock amplitude, 50% clock duty
cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
POWER DISSIPATION vs
COMMON-MODE REJECTION RATIO vs FREQUENCY SAMPLING FREQUENCY (DDR LVDS and CMOS)
Figure 85. Figure 86.
DRVDD current vs
SAMPLING FREQUENCY ACROSS LOAD CAPACITANCE
(CMOS)
Figure 87.
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Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142