Datasheet

www.ti.com
f
IN
− Input Frequency − MHz
60
64
68
72
76
80
84
88
92
96
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G061
Gain = 0 dB
Gain = 3.5 dB
f
IN
− Input Frequency − MHz
62
64
66
68
70
72
74
76
0 50 100 150 200 250 300 350 400 450 500
SNR − dBFS
G062
Gain = 0 dB
Gain = 3.5 dB
f
IN
− Input Frequency − MHz
60
65
70
75
80
85
90
95
0 100 200 300 400 500
SFDR − dBc
G063
Input adjusted to get −1dBFS input
1 dB
0 dB
5 dB
2 dB
3 dB
4 dB
6 dB
f
IN
− Input Frequency − MHz
60
62
64
66
68
70
72
74
76
0 100 200 300 400 500
SINAD − dBFS
G064
2 dB
5 dB
1 dB
0 dB
4 dB
6 dB
Input adjusted to get −1dBFS input
3 dB
AV
DD
− Supply Voltage − V
80
82
84
86
88
90
92
94
96
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SFDR − dBc
G065
SNR
SFDR
f
IN
= 70.1 MHz
DRV
DD
= 3.3 V
SNR − dBFS
72
73
74
75
76
77
78
79
80
SNR − dBFS
DRV
DD
− Supply Voltage − V
92
94
96
98
100
102
104
106
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SFDR − dBc
G066
f
IN
= 10.1 MHz
AV
DD
= 3.3 V
SNR
SFDR
70
71
72
73
74
75
76
77
ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6142 (F
S
= 65 MSPS) (continued)
All plots are at 25 ° C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface) SNR vs INPUT FREQUENCY (LVDS interface)
Figure 69. Figure 70.
SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS
Figure 71. Figure 72.
PERFORMANCE vs AVDD PERFORMANCE vs DRVDD
Figure 73. Figure 74.
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142