Datasheet

www.ti.com
PIN CONFIGURATION (LVDS MODE)
PDN
DRVDD
AGND
INP
CLKOUTM
INM
CLKOUTP
AGND
AVDD AVDD
AGND
CLKP
CLKM
1
2
3
4
5
6
7
8
9 10 11 12 13
14 15 16
D12_D13_P D12_D13_M
D0_D1_P
D10_D11_P
D0_D1_M
D10_D11_M D8_D9_P D8_D9_M
RESET
D6_D7_P
SCLK
D6_D7_M
SDATA
D4_D5_P
SEN
D4_D5_M
D2_D3_P
D2_D3_M
24
23
22
21
20
19
18
17
31 30 29 28 27 26 25
PadConnected To
DRGND
32
VCM
ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
RHB PACKAGE
(TOP VIEW)
Figure 8. LVDS Mode Pinout
PIN ASSIGNMENTS – LVDS Mode
PIN PIN NUMBER
PIN NAME DESCRIPTION
TYPE NUMBER OF PINS
AVDD Analog power supply I 13, 15 2
AGND Analog ground I 6, 9, 12 3
CLKP, CLKM Differential clock inputs I 7, 8 2
INP, INM Differential analog inputs I 10, 11 2
Internal reference mode – common-mode voltage output.
VCM External reference mode – reference input. The voltage forced on this pin sets the I/O 14 1
internal references.
Serial interface RESET input.
When using serial interface mode, the user MUST initialize the internal registers
through a hardware RESET by applying a high-going pulse on this pin or by using the
RESET software reset option. See the SERIAL INTERFACE section. I 2 1
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SCLK, SDATA, and SEN are used as parallel pin controls in this mode.)
The pin has an internal 100-k Ω pull-down resistor.
This pin functions as the serial interface clock input when RESET is low.
When RESET is tied high, it controls coarse gain and internal/external reference
SCLK selection. Tie SCLK low for internal reference and 0 dB gain and high for internal I 3 1
reference and 3.5 dB gain. See Table 1 .
The pin has an internal 100-k Ω pull-down resistor.
This pin functions as the serial interface data input when RESET is low. It controls
various power down modes along with the PDN pin when RESET is tied high.
SDATA I 4 1
See Table 3 for detailed information.
The pin has an internal 100 k Ω pull-down resistor.
The pin functions as the serial interface enable input when RESET is low. When
SEN RESET is high, it controls output interface type and data formats. See Table 2 for I 5 1
detailed information. The pin has an internal 100-k Ω pull-up resistor to DRVDD.
PDN Global power-down control pin I 16 1
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142