Datasheet

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PIN CONFIGURATION (CMOS MODE)
PDN
DRVDD
AGND
INP
OVR
INM
CLKOUT
AGND
A
VDD
AVDD
AGND
CLKP
CLKM
1
2
3
4
5
6
7
8
9 10 11 12 13
14 15 16
D13 D12
D1
D11
D0
D10 D9 D8
RESET
D7
SCLK
D6
SDATA
D5
SEN
D4
D3
D2
24
23
22
21
20
19
18
17
31 30 29
28 27 26 25
PadConnected To
DRGND
32
VCM
ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
RHB PACKAGE
(TOP VIEW)
Figure 7. CMOS Mode Pinout
PIN ASSIGNMENTS – CMOS Mode
PIN PIN NUMBER
PIN NAME DESCRIPTION
TYPE NUMBER OF PINS
AVDD Analog power supply I 13, 15 2
AGND Analog ground I 6, 9, 12 3
CLKP, CLKM Differential clock inputs I 7, 8 2
INP, INM Differential analog inputs I 10, 11 2
Internal reference mode – common-mode voltage output.
VCM External reference mode – reference input. The voltage forced on this pin sets the I/O 14 1
internal references.
Serial interface RESET input.
When using serial interface mode, the user MUST initialize the internal registers
through a hardware RESET by applying a high-going pulse on this pin, or by using
RESET the software reset option. See the SERIAL INTERFACE section. I 2 1
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SCLK, SDATA, and SEN are used as parallel pin controls in this mode.)
The pin has an internal 100-k Ω pull-down resistor.
This pin functions as the serial interface clock input when RESET is low.
When RESET is tied high, it controls coarse gain and internal/external reference
SCLK selection. Tie SCLK low for internal reference and 0 dB gain and high for internal I 3 1
reference and 3.5 dB gain. See Table 1 .
The pin has an internal 100-k Ω pull-down resistor.
This pin functions as the serial interface data input when RESET is low. It controls
various power down modes along with the PDN pin when RESET is tied high.
SDATA I 4 1
See Table 3 for detailed information.
The pin has an internal 100-k Ω pull-down resistor.
This pin functions as the serial interface enable input when RESET is low. When
RESET is high, it controls output interface type and data formats. See Table 2 for
SEN I 5 1
detailed information.
The pin has an internal 100-k Ω pull-up resistor to DRVDD.
PDN Global power-down control pin I 16 1
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Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142