Datasheet

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ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
Table 8.
A4 – A0
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(hex)
0A <DF> 0 0 <TEST PATTERNS> 0 0 0 0 0
2s Complement or straight
binary
D7-D5 Test patterns
000 Normal operation - <D13:D0> = ADC output
001 All zeros - <D13:D0> = 0x0000
010 All ones - <D13:D0> = 0x3FFF
011 Toggle pattern - <D13:D0> toggles between 0x2AAA and 0x1555
100 Digital ramp - <D13:D0> increments from 0x0000 to 0x3FFF by one code every cycle
101 Custom pattern - <D13:D0> = contents of CUSTOM PATTERN registers
110 Unused
111 Unused
D10 <DATA FORMAT>
0 2s Complement
1 Straight binary
Table 9.
A4 – A0
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(hex)
0B <CUSTOM LOW> 0 0
Lower 9 bits of custom pattern
Table 10.
A4 – A0
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(hex)
0C <FINE GAIN> 0 0 0 <CUSTOM HIGH>
Fine gain 0 to 6dB Upper 5 bits of custom pattern
Reg 0B <CUSTOM LOW> - Specifies lower 9 bits of custom pattern
D10-D2
Reg 0C <CUSTOM HIGH> - Specifies upper 5 bits of custom pattern
D4-D0
D10-D8 <FINE GAIN> Gain programming
000 0 dB Gain
001 1 dB Gain
010 2 dB Gain
011 3 dB Gain
100 4 dB Gain
101 5 dB Gain
110 6 dB Gain
111 Unused
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