Datasheet

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ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
Table 6.
A4 – A0
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(hex)
04 <DATAOUT POSN> <CLKOUT EDGE> <CLKOUT POSN> 0 0 0 0 0 0 0 0
Output data position Output Clock edge Output clock
control control position control
D8 <CLKOUT POSN> Output clock position control
0 Default output clock position after reset. The setup/hold timings for this clock position are specified
in the timing specifications table.
1 Output clock shifted (delayed) by 400 ps
D9 <CLKOUT EDGE>
0 Use rising edge to capture data
1 Use falling edge to capture data
D10 <DATAOUT_POSN>
0 Default position (after reset)
1 Data transition delayed by half clock cycle with respect to default position
Table 7.
A4 – A0
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(hex)
09 Bit-wise or 0 0 0 0 0 0 0 0 0 0
Byte-wise control
D10 Bit-wise or byte-wise selection (DDR LVDS mode only)
0 Bit-wise sequence - Even data bits (D0, D2, D4,..D12) are output at the rising edge of CLKOUTP
and odd data bits (D1, D3, D5,..D13) at the falling edge of CLKOUTP
1 Byte-wise sequence - Lower 7 data bits (D0-D7) are output at the rising edge of CLKOUTP and
upper 7 data bits (D8-D13) at the falling edge of CLKOUTP
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