Datasheet
www.ti.com
SERIAL INTERFACE
SCLK
SEN
A 4 A3 A 2 A 1 A 0 D10 D9 D 8 D 7 D6 D5 D4 D3 D2 D1 D0
REGISTER ADDRESS REGISTERDATA
SDATA
RESET
t
SCLK
t
DSU
t
DH
t
SLOADS
t
SLOADH
REGISTER INITIALIZATION
ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
Table 3. SDATA, PDN (Digital Control Pins)
SDATA PDN DESCRIPTION
Low Low Normal operation
Low High (AVDD) Standby - only the ADC is powered down
High (AVDD) Low Output buffers are powered down, fast wake-up time
High (AVDD) High (AVDD) Global power down. ADC, internal reference, and output buffers are powered down, slow wake-up time
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 5 bits form the register address and the remaining 11 bits form the register data.
The interface can work with a SCLK frequency from 20 MHz down to very low speeds (a few hertz) and also with
a non-50% SCLK duty cycle.
Figure 5. Serial Interface Timing Diagram
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:
1. Either through a hardware reset by applying a high-going pulse on the RESET pin (width greater than 10 ns)
as shown in Figure 5 .
OR
2. By applying a software reset. Using the serial interface, set the <RST> bit (D4 in register 0x00) to high. This
initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case
the RESET pin is kept low.
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142