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O O O O O O O OO O
E E E E E E E EE E
Input
Clock
CLKOUTM
CLKOUTP
OutputData
DXP,DXM
DDR
LVDS
N–9
N–8 N–7 N–6
N–5
N–1
N
N+1 N+2
N–9
N–8 N–7 N–6 N–5 N N+2
9ClockCycles
9ClockCycles
CLKOUT
OutputData
D0–D13
Parallel
CMOS
Input
Signal
Sample
N
N+1
N+2
N+3
N+4
t
h
t
PDI
t
a
t
su
t
h
t
PDI
CLKP
CLKM
N+9
N+10
N+11
N+12
t
su
E – EvenBitsD0,D2,D4,D6,D8,D10,D12
O – OddBitsD1,D3,D5,D7,D9,D11,D13
N+1N–1
Input
Clock
Output
Clock
Output
DataPair
CLKM
CLKOUTP
Dn_Dn+1_P,
Dn_Dn+1_M
CLKP
t
PDI
t
su
t
h
t
h
t
su
CLKOUTM
(1)
Dn – BitsD0,D2,D4,D6,D8,D10,D12
(2)
Dn+1 – BitsD1,D3,D5,D7,D9,D11,D13
Dn
(1)
Dn+1
(2)
Input
Clock
Output
Clock
Output
Data
CLKM
Dn
CLKP
t
PDI
t
su
t
h
CLKOUT
(1)
Dn – BitsD0–D13
Dn
(1)
ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
Figure 1. Latency
Figure 2. LVDS Mode Timing
Figure 3. CMOS Mode Timing
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Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142