Datasheet

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ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data
sheet.
ADS6145 ADS6144 ADS6143 ADS6142
F
S
= 125 MSPS F
S
= 105 MSPS F
S
= 80 MSPS F
S
= 65 MSPS
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Clock Input clock rising edge
t
PDI
propagation zero-cross to 50% of 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 ns
delay CLKOUT rising edge
Duty cycle of output
Output clock
clock (CLKOUT), 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55%
duty cycle
10 ≤ F
s
≤ 125 MSPS
Rise time measured
from 20% to 80% of
Data rise
DRVDD,
t
r
time,
Fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns
t
f
Data fall
from 80% to 20% of
time
DRVDD,
1 ≤ F
s
≤ 125 MSPS
Rise time measured
from 20% to 80% of
t
CLKRI
Output clock
DRVDD,
SE
rise time,
Fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns
t
CLKFA
Output clock
from 80% to 20% of
LL
fall time
DRVDD,
1 ≤ F
s
≤ 125 MSPS
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