Datasheet

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TIMING CHARACTERISTICS – LVDS AND CMOS MODES
(1)
ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
clock amplitude, C
L
= 5 pF
(2)
, I
O
= 3.5
mA, R
L
= 100 Ω
(3)
, no internal termination, unless otherwise noted.
For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data
sheet.
ADS6125 ADS6124 ADS6123 ADS6122
F
S
= 125 MSPS F
S
= 105 MSPS F
S
= 80 MSPS F
S
= 65 MSPS
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Aperture
t
a
0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns
delay
Aperture
t
j
150 150 150 150 fs rms
jitter
From global power
15 50 15 50 15 50 15 50 µ s
down
Wake-up
time From standby 15 50 15 50 15 50 15 50 µ s
(to valid
From output CMOS 100 200 100 200 100 200 100 200 ns
data)
buffer
LVDS 200 500 200 500 200 500 200 500 ns
disable
clock
Latency 9 9 9 9
cycles
DDR LVDS MODE
(4)
, DRVDD = 3.3 V
Data valid
(6)
to
Data setup
t
su
zero-cross of 1.7 2.3 2.5 3.1 3.9 4.5 5.4 6.0 ns
time
(5)
CLKOUTP
Zero-cross of
Data hold
t
h
CLKOUTP to data 0.7 1.7 0.7 1.7 0.7 1.7 0.7 1.7 ns
time
(5)
becoming invalid
(6)
Input clock rising edge
Clock
zero-cross to output
t
PDI
propagation 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 ns
clock rising edge
delay
zero-cross
Duty cycle of
LVDS bit differential clock,
clock duty (CLKOUTP- 40% 47% 55% 40% 47% 55% 40% 47% 55% 40% 47% 55%
cycle CLKOUTM)
10 ≤ Fs ≤ 125 MSPS
Rise time measured
Data rise
from – 50 mV to 50 mV
t
r
time,
Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps
t
f
Data fall
from 50 mV to – 50 mV
time
1 ≤ Fs ≤ 125 MSPS
Rise time measured
t
CLKRI
Output clock
from – 50 mV to 50 mV
SE
rise time,
Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps
t
CLKFA
Output clock
from 50 mV to – 50 mV
LL
fall time
1 ≤ Fs ≤ 125 MSPS
PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.3 V, default output buffer drive strength
(7)
Data setup Data valid
(8)
to 50% of
t
su
2.9 4.4 3.6 5.1 5.1 6.6 6.5 8.0 ns
time
(5)
CLKOUT rising edge
50% of CLKOUT
Data hold
t
h
Rising edge to data 1.3 2.7 2.1 3.5 3.6 5.0 5.1 6.5 ns
time
(5)
becoming invalid
(8)
Clock Input clock rising edge
t
PDI
propagation zero-cross to 50% of 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 ns
delay CLKOUT rising edge
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) C
L
is the Effective external single-ended load capacitance between each output pin and ground.
(3) I
O
Refers to the LVDS buffer current setting; R
L
is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6) Data valid refers to logic high of +100 mV and logic low of – 100 mV.
(7) For DRVDD < 2.2V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See
Parallel CMOS interface in application section.
(8) Data valid refers to logic high of 2V (1.7V) and logic low of 0.8 V (0.7V) for DRVDD = 3.3V (2.5V).
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