Datasheet

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DDR LVDS Interface

CLKOUTP

CLKOUTM

D0_D1_P

D0_D1_M

D2_D3_P

D2_D3_M

D4_D5_P

D4_D5_M

D6_D7_P

D6_D7_M

D8_D9_P

D8_D9_M

D10_D11_P

D10_D11_M

Output Clock

Data bits D0, D1

Data bits D2, D3

Data bits D4, D5

Data bits D6, D7

Data bits D8, D9

Data bits D10, D11

ADS612x

Pins

12-Bit ADC Data

LVDS Buffers

ADS6125, ADS6124

ADS6123, ADS6122

SLAS560A – OCTOBER 2007 – REVISED MARCH 2008

The LVDS interface works only with 3.3 V DRVDD supply. In this mode, the 12 data bits and the output clock are

available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output

on each LVDS differential pair every clock cycle (DDR - Double Data Rate, see Figure 102 ). So, there are 7

LVDS output pairs for the 12 data bits and 1 LVDS output pair for the output clock.

LVDS Buffer Current Programmability

The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω , this results in a 350-mV

single-ended voltage swing (700-mV

differential swing). The LVDS buffer currents can also be programmed to

2.5 mA, 4.5 mA, and 1.75 mA (register bits <LVDS CURRENT>, see Table 11 ). In addition, there is a current

double mode, where this current is doubled for the data and output clock buffers (register bits <CURRENT

DOUBLE>, see Table 11 ).

Figure 102. DDR LVDS Outputs

Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the rising edge of CLKOUTP and the odd data

bits D1, D3, D5, D7, D9, D11, and D13 are output at the falling edge of CLKOUTP. Both the rising and falling

edges of CLKOUTP must be used to capture all the 12 data bits (see Figure 103 ).

Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122