Datasheet

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DIGITAL OUTPUT INTERFACE

Parallel CMOS Interface

ADS6125, ADS6124

ADS6123, ADS6122

SLAS560A – OCTOBER 2007 – REVISED MARCH 2008

ADS612X outputs 12 data bits together with an output clock. The output interface are either parallel CMOS or

DDR LVDS voltage levels and can be selected using serial register bit <LVDS CMOS> or parallel pin SEN.

In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V

(typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle.

For DRVDD ≥ 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving

chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed

(125 MSPS). It is recommended to minimize the load capacitance seen by data and clock output pins by using

short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them.

For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired

setup/hold times).

Output Clock Position Programmability

There exists an option to shift (delay) the output clock position so that the setup time increases by 400 ps

(typical, with respect to the default timings specified). This may be useful if the receiver needs more setup time,

especially at high sampling frequencies. This can be programmed using the serial interface register bit

<CLKOUT_POSN> (see Table 6 ).

Output Buffer Strength Programmability

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of

sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made

stronger. To minimize this, the ADS612X CMOS output buffers are designed with controlled drive strength to get

best SNR. The default drive strength also ensures wide data stable window for load capacitances upto 5 pF and

DRVDD supply voltage ≥ 2.2 V.

To ensure wide data stable window for load capacitance > 5 pF, there is an option to increase the drive strength

using the serial interface ( <DRIVE STRENGTH>, see Table 12 ). Note that for DRVDD supply voltage < 2.2 V, it

is recommended to use maximum drive strength (for any value of load capacitance).

CMOS Mode Power Dissipation

With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every

output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock

cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined

by the average number of output bits switching, which is a function of the sampling frequency and the nature of

the analog input signal.

Digital current due to CMOS output switching = C

× DRVDD x (N x F

AVG

)

where C

= load capacitance, N × F

AVG

= average number of output bits switching

Figure 84 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input

frequency.

Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122