Datasheet

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CLOCK INPUT

CLKP

5 kW

VCM

5 kW

6 pF

10 W

CLKM

Clock Buffer

Ceq

Ceq 1 to 3 pF, equivalent input capacitance of clock buffer»

Lpkg

1 nH»

Lpkg

1 nH»

Cbond

1 pF»

Cbond

1 pF»

Resr

100» W

Resr

100» W

ADS6125, ADS6124

ADS6123, ADS6122

SLAS560A – OCTOBER 2007 – REVISED MARCH 2008

The clock inputs of the ADS612X can be driven differentially (SINE, LVPECL or LVDS) or single-ended

(LVCMOS), with little or no difference in performance between configurations. The common-mode voltage of the

clock inputs is set to VCM using internal 5-k Ω resistors as shown in Figure 97 . This allows the use of

transformer-coupled drive circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources

(Figure 99 and Figure 100 ).

For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to

common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with

0.1- µ F capacitors, as shown in Figure 99 . A single-ended CMOS clock can be ac-coupled to the CLKP input,

with CLKM connected to ground with a 0.1- µ F capacitor, as shown in Figure 100 .

For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass filtering

of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty

cycle clock input. Figure 24 shows the performance of the ADC versus clock duty cycle.

Figure 97. Internal Clock Buffer

Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122