Datasheet
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APPLICATION INFORMATION
THEORY OF OPERATION
ANALOG INPUT
Resr
200 W
Lpkg
nH»1
25 W
Sampling
Capacitor
Csamp
4.0pF
INP
INM
Cbond
pF»1
50 W
Cpar1
0.8pF
Cpar2
1pF
Ron
15 W
Ron
10 W
Ron
15 W
Cpar2
1pF
50 W
3.2pF
Lpkg
1nH»
25 W
Cbond
pF»1
Resr
200 W
Csamp
4.0pF
Sampling
Capacitor
Sampling
Switch
Sampling
Switch
RCRFilter
ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
ADS612X is a family of low power 12-bit pipeline ADC in a CMOS process up to 125 MSPS sampling frequency.
It is based on switched capacitor technology and runs off a single 3.3-V supply. The conversion process is
initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold,
the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a
digital correction logic block. At every clock edge, the sample propagates through the pipeline resulting in a data
latency of 9 clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either
straight offset binary or binary 2s complement format.
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 89 .
This differential topology results in good ac-performance even for high input frequencies at high sampling rates.
The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on VCM
pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V
and VCM – 0.5 V, resulting in a 2-V
PP
differential input swing. The maximum swing is determined by the internal
reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Figure 89. Input Stage
The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins
to the voltage across the sampling capacitors).
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122