Datasheet

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RECOMMENDED OPERATING CONDITIONS
ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage 3 3.3 3.6 V
CMOS Interface 1.65 1.8 to 3.3 3.6 V
DRVDD Output buffer supply voltage
(1)
LVDS Interface 3 3.3 3.6 V
ANALOG INPUTS
Differential input voltage range 2 V
pp
V
IC
Input common-mode voltage 1.5 ± 0.1 V
Voltage applied on VCM in external reference mode 1.45 1.5 1.55 V
CLOCK INPUT
ADS6125 1 125
ADS6124 1 105
F
S
Input clock sample rate MSPS
ADS6123 1 80
ADS6122 1 65
Sine wave, ac-Coupled 0.4 1.5
LVPECL, ac-Coupled ± 0.8
Input clock amplitude differential
V
pp
(V
CLKP
– V
CLKM
)
LVDS, ac-Coupled ± 0.35
LVCMOS, ac-Coupled 3.3
Input Clock duty cycle 35% 50% 65%
DIGITAL OUTPUTS
For C
LOAD
≤ 5 pF and DRVDD ≥ 2.2 DEFAULT
V strength
For C
LOAD
> 5 pF and DRVDD ≥ 2.2 MAXIMUM
Output buffer drive strength
(2)
V strength
MAXIMUM
For DRVDD < 2.2 V
strength
CMOS Interface, maximum buffer 10
strength
Maximum external load capacitance from each LVDS Interface, without internal 5
C
LOAD
pF
output pin to DRGND termination
LVDS Interface, with internal 10
termination
R
LOAD
Differential load resistance (external) between the LVDS output pairs 100 Ω
T
A
Operating free-air temperature -40 85 ° C
(1) For easy migration to next generation, higher sampling speed devices (> 125 MSPS), use 1.8V DRVDD supply.
(2) See Output Buffer Strength Programmability in application section
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122