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f
IN
− Input Frequency − MHz
60
64
68
72
76
80
84
88
92
96
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G043
Gain = 0 dB
Gain = 3.5 dB
f
IN
− Input Frequency − MHz
62
64
66
68
70
72
74
76
0 50 100 150 200 250 300 350 400 450 500
SNR − dBFS
G044
Gain = 0 dB
Gain = 3.5 dB
f
IN
− Input Frequency − MHz
60
65
70
75
80
85
90
95
0 100 200 300 400 500
SFDR − dBc
G045
Input adjusted to get −1dBFS input
1 dB
0 dB
5 dB
6 dB2 dB
3 dB
4 dB
f
IN
− Input Frequency − MHz
58
60
62
64
66
68
70
72
74
0 100 200 300 400 500
SINAD − dBFS
G046
2 dB
5 dB
1 dB
0 dB
3 dB
4 dB
Input adjusted to get −1dBFS input
6 dB
SNR − dBFS
DRV
DD
− Supply Voltage − V
88
90
92
94
96
98
100
102
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SFDR − dBc
G048
f
IN
= 10.1 MHz
AV
DD
= 3.3 V
SNR
SFDR
67
68
69
70
71
72
73
74
AV
DD
− Supply Voltage − V
72
74
76
78
80
82
84
86
88
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SFDR − dBc
G047
f
IN
= 70.1 MHz
DRV
DD
= 3.3 V
SNR − dBFS
70
71
72
73
74
75
76
77
78
SNR
SFDR
ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6123 (F
S
= 80 MSPS) (continued)
All plots are at 25 ° C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
differential
clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface) SNR vs INPUT FREQUENCY (LVDS interface)
Figure 50. Figure 51.
SFDR vs INPUT FREQUENCY ACROSS GAINS SINAD vs INPUT FREQUENCY ACROSS GAINS
Figure 52. Figure 53.
PERFORMANCE vs AVDD PERFORMANCE vs DRVDD
Figure 54. Figure 55.
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122