Datasheet

www.ti.com

DESCRIPTION OF SERIAL REGISTERS

ADS6125, ADS6124

ADS6123, ADS6122

SLAS560A – OCTOBER 2007 – REVISED MARCH 2008

Each register function is explained in detail below.

Table 5.

A4 – A0

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

(hex)

00 <PDN OBUF> <COARSE <LVDS CMOS> 0 0 <REF> <RST> 0 <PDN CLKOUT> 0 <STBY>

Output buffers GAIN> LVDS or CMOS Internal or Software Output clock ADC Power

powered down Coarse gain output interface external Reset buffer powered down

reference down

D0 <STBY> Power down modes

0 Normal operation

1 Device enters standby mode where only ADC is powered down.

D2 <PDN CLKOUT> Power down modes

0 Output clock is active (on CLKOUT) pin

1 Output clock buffer is powered down and becomes tri-stated. Data outputs are unaffected.

D4 <RST>

1 Software reset applied - resets all internal registers and the bit self-clears to 0.

D5 <REF> Reference selection

0 Internal reference enabled

1 External reference enabled

D8 <LVDS CMOS> Output Interface selection

0 Parallel CMOS interface

1 DDR LVDS interface

D9 <COARSE GAIN> Gain programming

0 0 dB Coarse gain

1 3.5 dB Coarse gain

D10 <PDN OBUF> Power down modes

0 Output data and clock buffers enabled

1 Output data and clock buffers disabled

Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122