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SERIAL INTERFACE TIMING
RESET TIMING
t
1
t
3
t
2
PowerSupply
AVDD,DRVDD
RESET
SEN
ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
Typical values at 25 ° C, min and max values across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN TYP MAX UNIT
f
SCLK
SCLK Frequency = 1/t
SCLK
> DC 20 MHz
t
SLOADS
SEN to SCLK Setup time 25 ns
t
SLOADH
SCLK to SEN Hold time 25 ns
t
DSU
SDATA Setup time 25 ns
t
DH
SDATA Hold time 25 ns
Typical values at 25 ° C, min and max values across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active 5 ms
t
2
Reset pulse width Pulse width of active RESET signal 10 ns
t
3
Register write delay Delay from RESET disable to SEN active 25 ns
t
PO
Power-up time Delay from power-up of AVDD and DRVDD to output stable 6.5 ms
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122