Datasheet
www.ti.com
DEVICE PROGRAMMING MODES
USING SERIAL INTERFACE PROGRAMMING ONLY
USING PARALLEL INTERFACE CONTROL ONLY
(3/8) AVDD
(3/8) AVDD
ToParallelPin
(SCLK,SDATA,SEN)
3R
AVDD
AVDDGND
3R
2R
(5/8) AVDD
(5/8) AVDD
GND
ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
ADS612X has several features that can be easily configured using either parallel interface control or serial
interface programming.
To program using the serial interface, the internal registers must first be reset to their default values, and the
RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are
used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET
pin, or by a high setting on the <RST> bit (D4 in register 0x00). The Serial Interface section describes register
programming and register reset in more detail.
To control the device using parallel interface, keep RESET tied to high (AVDD). Now, SEN, SCLK, SDATA and
PDN function as parallel interface control pins. These pins can be used to directly control certain modes of the
ADC by connecting them to the correct voltage levels (as described in Table 1 to Table 3 ). There is no need to
apply a reset pulse.
Frequently used functions are controlled in this mode — standby, selection between LVDS/CMOS output format,
internal/external reference and 2s complement/straight binary output format. Table 1 ,Table 2 , and Table 3
describe the modes controlled by the parallel pins.
Figure 4. Simple Scheme to Configure Parallel Pins
DESCRIPTION OF PARALLEL PINS
Table 1. SCLK Control Pin
SCLK DESCRIPTION
0 Internal reference and 0 dB gain (Full-scale = 2 V
PP
)
(3/8) AVDD External reference and 0 dB gain (Full-scale = 2 V
PP
)
(5/8) AVDD External reference and 3.5 dB coarse gain (Full-scale = 1.34 V
PP
)
AVDD Internal reference and 3.5 dB coarse gain (Full-scale = 1.34 V
PP
)
Table 2. SEN Control Pin
SEN DESCRIPTION
0 2s Complement format and DDR LVDS interface
(3/8) AVDD Straight binary format and DDR LVDS interface
(5/8) AVDD Straight binary and parallel CMOS interface
AVDD 2s Complement format and parallel CMOS interface
12 Submit Documentation Feedback Copyright © 2007 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122