Datasheet

www.ti.com
ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data
sheet.
ADS6125 ADS6124 ADS6123 ADS6122
F
S
= 125 MSPS F
S
= 105 MSPS F
S
= 80 MSPS F
S
= 65 MSPS
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Duty cycle of output
Output clock
clock (CLKOUT) 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55%
duty cycle
10 ≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
Data rise
DRVDD
t
r
time,
Fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns
t
f
Data fall
from 80% to 20% of
time
DRVDD
1 ≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
t
CLKRI
Output clock
DRVDD
SE
rise time,
Fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns
t
CLKFA
Output clock
from 80% to 20% of
LL
fall time
DRVDD
1 ≤ Fs ≤ 125 MSPS
10 Submit Documentation Feedback Copyright © 2007 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122