Datasheet

Basic Test Procedure

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– Use a high quality, low phase noise generator for this input to ensure proper device evaluation.

• Enable SNR Boost (if desired)

– Hardware enable by SNRBoost pins, JP11 and JP13

• Set Digital Funct Ctrl to "Gain Enabled"

• Select desired SNRBoost Filter Chx register

• Set Digital Funct Ctrl to "Gain Disabled"

• Use Hardware pins at jumper JP11 and JP13 to turn on/off SNR Boost for each pair of channels

– Software enable by setting the GUI registers only

• Set Digital Funct Ctrl to "Gain Enabled"

• Set desired SNRBoost Chx to On

• Select desired SNRBoost Filter Chx register

• Set Digital Funct Ctrl to "Gain Disabled"

• Set Override SNRb Pins on Advanced Tab to On

• Initiate a capture by pressing the Capture button on the TSW1200 GUI.

2.6 ADS58C48 Performance Results

Figure 7 shows the performance results with the SNR Boost disabled at 200 MSPS clock frequency and

with a 149 MHz input tone. Figure 8 shows the same set-up with SNR Boost enabled using a filter register

setting of 40 (BW = 60 × Fs/184 MHz; CF = 46 × Fs/184 MHz) corresponding roughly to 60 MHz of BW for

the given clocking rate. ADC calculations related to SNR and SFDR are completed over this specified

bandwidth.

Figure 7. FFT Plot: 200 MHz Clock, 149 MHz input; SNRBOOST Disable

ADS58C48EVM SLAU313–May 2010