Datasheet

ADS58B18
ADS58B19
www.ti.com SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2010) to Revision D Page
• Changed documet status to production data ........................................................................................................................ 1
• Updated status of ADS58B19 to production data throughout document .............................................................................. 1
• Updated document format to current standards ................................................................................................................... 1
• Changed Clock Input, Input clock sample rate parameters for both ADS58B18 and ADS58B19 in Recommended
Operating Conditions table ................................................................................................................................................... 3
• Added footnote 3 to Recommended Operating Conditions table ......................................................................................... 3
• Changed conditions of ADC latency parameter in Timing Requirements table ................................................................. 15
• Deleted footnote 7 from Timing Requirements table .......................................................................................................... 15
• Deleted footnote 10 in Timing Requirements tableα .......................................................................................................... 16
• Deleted table 2 (CMOS Timing Across Sampling Frequencies, withe respect to output clock) and table 4 (CMOS
Timing Across Sampling Frequencies, withe respect to input clock) ................................................................................. 17
• Changed titles of Table 2 and Table 3 ............................................................................................................................... 17
• Updated Figure 8 ................................................................................................................................................................ 18
• Changed description of logic high in Table 6 ..................................................................................................................... 20
• Updated bit D3 of registers 25 and 42 and added register DF to Table 8 ......................................................................... 23
• Changed bit 3 and description of bits 2 to 0 in Register Address 25h ............................................................................... 25
• Changed description of bit 4 in Register Address 3Dh ....................................................................................................... 26
• Changed bit 3 of register address 42h ............................................................................................................................... 28
• Added Register Address DFh to Description of Serial Registers section ........................................................................... 31
• Updated conditions of Typical Characteristics: ADS58B18 ................................................................................................ 32
• Updated Figure 36 .............................................................................................................................................................. 37
• Updated conditions of Typical Characteristics: ADS58B19 ................................................................................................ 38
• Updated Figure 53 .............................................................................................................................................................. 42
• Updated conditions of Typical Characteristics: General ..................................................................................................... 43
• Deleted Digital Functions and Low-Latency Mode section ................................................................................................. 48
• Changed SNRBoost enable description in SNR Enhancement Using SNRBoost section ................................................. 49
• Changed reset description in Gain for SFDR/SNR Trade-Off section ................................................................................ 50
• Changed reset description in Offset Correction section ..................................................................................................... 51
Changes from Revision B (July 2010) to Revision C Page
• Changed Analog Inputs, Input common-mode voltage typical specification in Recommended Operating Conditions
table ...................................................................................................................................................................................... 3
• Added Clock Input, Input clock duty cycle minimum and maximum specifiations to Recommended Operating
Conditions table .................................................................................................................................................................... 3
• Updated format of Typical Characteristics graphs .............................................................................................................. 32
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