Datasheet

ADS58B18

ADS58B19

SBAS487D – NOVEMBER 2009– REVISED JANUARY 2011

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Input Over-Voltage Indication (OVR_SDOUT Pin)

The device has an OVR_SDOUT pin that provides information about analog input overload (as long as the

READOUT register bit is '0'). When the READOUT bit is '1', it functions as a serial readout pin.

At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin

goes high. The OVR remains high as long as the overload condition persists. The OVR pin is a CMOS output

buffer (running off DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS).

For a positive overload, the D[10:0] output data bits are 7FFh in offset binary output format and 3FFh in twos

complement output format. For a negative input overload, the output code is 000h in offset binary output format

and 400h in twos complement output format.

Output Data Format

Two output data formats are supported: twos complement and offset binary. They can be selected using the

DATA FORMAT serial interface register bit or using the DFS pin.

BOARD DESIGN CONSIDERATIONS

Grounding

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of

the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout

and grounding.

Supply Decoupling

Because the ADS58B18/19 already include internal decoupling, minimal external decoupling can be used without

loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum

number of capacitors depends on the actual application. The decoupling capacitors should be placed very close

to the converter supply pins.

Exposed Pad

In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the

digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and

electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and

QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com).

Product Folder Link(s): ADS58B18 ADS58B19