Datasheet

CMOSOutputBuffers
9-/11-BitADCData
ADS58B1x
CLKOUT
D0
D1
D2
CLKIN
D0_In
D1_In
D2_In
UseExternalClockBuffer
(>200MSPS)
Useshorttracesbetween
ADCoutputandreceiverpins(1to2inches).
Flip-Flops
Receiver(FPGA,ASIC,etc.)
InputClock
ADS58B18
ADS58B19
www.ti.com SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011
Figure 74. CMOS Capture Example
CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital Current as a Result of CMOS Output Switching = C
L
× DRVDD × (N × f
AVG
)
where:
C
L
= load capacitance,
N × F
AVG
= average number of output bits switching. (1)
© 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 57
Product Folder Link(s): ADS58B18 ADS58B19