Datasheet

CLKOUT

OVR_SDOUT

Pins

ADS58B18

CMOSOutputBuffers

11-Bit

ADCData

D10

ADS58B18

ADS58B19

SBAS487D – NOVEMBER 2009– REVISED JANUARY 2011

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Parallel CMOS Interface

In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The

rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 73 depicts the CMOS

output interface.

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.

The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this

degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength

ensures a wide data stable window (even at 250MSPS) is provided so the data outputs have minimal load

capacitance. It is recommended to use short traces (1 to 2 inches, or 2,54cm to 5,08cm) terminated with less

than 5pF load capacitance, as shown in Figure 74.

For sampling frequencies greater than 200MSPS, it is recommended to use an external clock to capture data.

The delay from input clock to output data and the data valid times are specified for higher sampling frequencies.

These timings can be used to delay the input clock appropriately and use it to capture data.

Figure 73. CMOS Output Interface

Product Folder Link(s): ADS58B18 ADS58B19