Datasheet

D7_D8_M
D7_D8_P
D5_D6_M
D5_D6_P
D3_D4_M
D3_D4_P
D1_D2_M
D1_D2_P
D0_M
D0_P
CLKOUTM
DataBitsD7,D8
DataBitsD5,D6
DataBitsD3,D4
DataBitsD1,D2
DataBitsD0
OutputClock
CLKOUTP
Pins
ADS58B19
LVDSBuffers
9-Bit
ADCData
D9_D10_M
D9_D10_P
D7_D8_M
D7_D8_P
D5_D6_M
D5_D6_P
D3_D4_M
D3_D4_P
D1_D2_M
D1_D2_P
D0_M
D0_P
CLKOUTM
DataBitsD9,D10
DataBitsD7,D8
DataBitsD5,D6
DataBitsD3,D4
DataBitsD1,D2
DataBitsD0
OutputClock
CLKOUTP
Pins
ADS58B18
LVDSBuffers
11-Bit
ADCData
ADS58B18
ADS58B19
www.ti.com SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011
DDR LVDS Outputs
In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 67 and Figure 68. Two bit order
options are available: bit-wise sequence (default) and byte-wise sequence. Byte-wise sequence can be
programmed with the BYTE-WISE En Register bit.
Figure 67. ADS58B18 LVDS Outputs
Figure 68. ADS58B19 LVDS Outputs
Bit-Wise Sequence
Even data bits (D0, D2, D4, etc) are output at the rising edge of CLKOUTP and the odd data bits (D1, D3, D5,
etc) are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to
capture all the data bits; see Figure 69.
Byte-Wise Sequence
In the ADS58B18, data bits D[0:4] are output at the falling edge of CLKOUTP and data bits D[5:10] are output at
the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all the data
bits; see Figure 70.
In the ADS58B19, data bits D[0:3] are output at the falling edge of CLKOUTP and data bits D[4:8] are output at
the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all the data
bits; see Figure 71.
© 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 53
Product Folder Link(s): ADS58B18 ADS58B19