Datasheet

ADS58B18

ADS58B19

SBAS487D – NOVEMBER 2009– REVISED JANUARY 2011

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POWER DOWN

The ADS58B18/19 has three power-down modes: power-down global, standby, and output buffer disable.

Power-Down Global

In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down,

resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state.

The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To

enter the global power-down mode, set the PDN GLOBAL register bit.

Standby

In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up

time of 5µs. The total power dissipation in standby mode is approximately 185mW. To enter the standby mode,

set the STANDBY register bit.

Output Buffer Disable

The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast,

approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin.

Input Clock Stop

In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The

power dissipation is approximately 80mW.

POWER-SUPPLY SEQUENCE

During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are

separated in the device. Externally, they can be driven from separate supplies or from a single supply.

DIGITAL OUTPUT INFORMATION

The ADS58B18/19 provide either 11-bit or 9-bit data and an output clock synchronized with the data.

Output Interface

Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. The output can be

selected using the LVDS CMOS serial interface register bit or using the DFS pin. The DFS pin has higher priority

for deciding the type of interface, unless the LVDS CMOS override bit is set.

Product Folder Link(s): ADS58B18 ADS58B19