Datasheet

ADS58B18

ADS58B19

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SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011

OFFSET CORRECTION

The ADS58B18/19 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV.

The correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the

algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the

correction loop is a function of the sampling clock frequency. The time constant can be controlled using the

OFFSET CORR TIME CONSTANT register bits, as described in Table 12.

Table 12. Time Constant of Offset Correction Loop

TIME CONSTANT, TC

CLK

OFFSET CORR TIME CONSTANT (Number of Clock Cycles) TIME CONSTANT, TC

CLK

× 1/f

(sec)

(1)

0000 1M 5ms

0001 2M 10.5ms

0010 4M 21ms

0011 8M 42ms

0100 16M 84ms

0101 32M 168ms

0110 64M 336ms

0111 128M 671ms

1000 256M 1.34s

1001 512M 2.68s

1010 1G 5.37s

1011 2G 10.7s

1100 Reserved —

1101 Reserved —

1110 Reserved —

1111 Reserved —

(1) Sampling frequency, f

= 250MSPS.

After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen,

the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is

disabled by default after reset.

After a reset, the device is in low-latency disabled mode. To use offset correction, set ENABLE OFFSET CORR

to '1' and program the required time constant.

Product Folder Link(s): ADS58B18 ADS58B19