Datasheet

CLKP
0.95V
5kW
5kW
2pF
20W
L
1nH
PKG
C
1pF
BOND
R
100W
ESR
CLKM
C ockl Bufef r
C
EQ
20W
L
1nH
PKG
C
1pF
BOND
R
100W
ESR
C
EQ
0.1mF
0.1mF
CLKP
VCM
CLKM
CMOS
ClockInput
0.1mF
0.1mF
CLKP
CLKM
DifferentialSine-Wave,
PECL,orLVDS
ClockInput
ADS58B18
ADS58B19
www.ti.com SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011
CLOCK INPUT
The ADS58B18/19 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance. The common-mode voltage of the clock inputs is set to VCM using
internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or
ac-coupling for LVPECL and LVDS clock sources. Figure 63 shows a circuit for the internal clock buffer.
NOTE: C
EQ
is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
Figure 63. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1μF
capacitor, as shown in Figure 64. For best performance, the clock inputs must be driven differentially, reducing
susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock
source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no
change in performance with a non-50% duty cycle clock input (see Figure 34). Figure 65 shows a differential
circuit.
Figure 64. Single-Ended Clock Driving Circuit
Figure 65. Differential Clock Driving Circuit
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Product Folder Link(s): ADS58B18 ADS58B19