Datasheet

35 40 45 50 55 60 65
75
80
85
90
95
65
65.5
66
66.5
67
Input Clock Duty Cycle (%)
THD (dBc)
SNR (dBFS)
THD
SNR
Input Frequency = 10MHz
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
0 20 40 60 80 100 120 140 160 180 200
Sampling Speed (MSPS)
Analog Power (mW)
Includes AVDD and AVDD_BUF Power
40
50
60
70
80
90
100
110
0 20 40 60 80 100 120 140 160 180 200
Sampling Speed (MSPS)
DRVDD Power (mW)
Default
With SNRBoost Enable
ADS58B18
ADS58B19
www.ti.com SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS58B18 (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5V
PP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE ANALOG POWER vs SAMPLING FREQUENCY
Figure 34. Figure 35.
DRVDD POWER vs SAMPLING FREQUENCY
Figure 36.
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Product Folder Link(s): ADS58B18 ADS58B19