Datasheet

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SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011

7 6 5 4 3 2 1 0

0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING

Bit 7 Always write '0'

Bit 6 PDN GLOBAL: Power-down

This bit sets the state of operation.

0 = Normal operation

1 = Total power down; the ADC, internal references, and output buffers are powered down; slow

wake-up time.

Bit 5 Always write '0'

Bit 4 PDN OBUF: Power-down output buffer

This bit set the output buffer.

0 = Output buffer enabled

1 = Output buffer powered down

Bits[3:2] Always write '0'

Bits[1:0] EN LVDS SWING: LVDS swing control

00 = LVDS swing control using LVDS SWING register bits is disabled

01 = Do not use

10 = Do not use

11 = LVDS swing control using LVDS SWING register bits is enabled

7 6 5 4 3 2 1 0

OFFSET PEDESTAL 0 0 0 0 0

Bits[7:5] OFFSET PEDESTAL

These bits set the offset pedestal.

When the offset correction is enabled, the final converged value after the offset is corrected is the

ADC mid-code value. A pedestal can be added to the final converged value by programming these

bits.

011 = +3 LSB

010 = +2 LSB

001 = +1 LSB

000 = 0 LSB

111 = –1 LSB

110 = –2 LSB

101 = –3 LSB

100 = –4 LSB

Bits[4:0] Always write '0'

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