Datasheet

ADS58B18
ADS58B19
SBAS487D – NOVEMBER 2009– REVISED JANUARY 2011 www.ti.com
Register Address 42h (Default = 00h)
7 6 5 4 3 2 1 0
DIS LOW
CLKOUT FALL POSN 0 0 STBY 0 BYTE-WISE En
LATENCY
Bits[7:6] CLKOUT FALL POSN
These bits control the position of the output clock falling edge.
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 400ps, hold increases by 400ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200ps, hold increases by 200ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Falling edge is advanced by 100ps
10 = Falling edge is advanced by 200ps
11 = Falling edge is advanced by 1.5ns
Bits[5:4] Always write '0'
Bit 3 DIS LOW LATENCY: Disable low latency
This bit controls the low-latency mode.
0 = Recommended not to use this mode.
1 = After reset, the low-latency mode is disabled and 0dB gain is enabled.
Bit 2 STBY: Standby mode
This bit sets the standby mode.
0 = Normal operation
1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time
from standby is fast
Bit 1 Always write '0'
Bit 0 BYTE-WISE En: Output data enable
0 = The output data bit sequence is bit-wise (see Figure 22).
1 = The output data bit sequence is byte-wise (see Figure 23 and Figure 24).
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