Datasheet

ADS58B18

ADS58B19

www.ti.com

SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011

7 6 5 4 3 2 1 0

GAIN 0 TEST PATTERNS

Bits[7:4] GAIN: Gain programmability

These bits set the gain programmability in 0.5dB steps.

0000 = 0dB gain (default after reset)

0110 = 0.5dB gain

0111 = 1dB gain

1000 = 1.5dB gain

1001 = 2dB gain

1010 = 2.5dB gain

1011 = 3dB gain

1100 = 3.5dB gain

Bit 3 Always write '0'

Bits[2:0] TEST PATTERNS: Data capture

These bits can be used to verify data capture.

000 = Normal operation

001 = Outputs all 0s

010 = Outputs all 1s

011 = Outputs toggle pattern

In the ADS58B18, output data D[10:0] are an alternating sequence of 01010101010 and

10101010101.

In the ADS58B19, output data D[8:0] are an alternating sequence of 010101010 and 101010101.

100 = Outputs digital ramp

Output data increments by one LSB (11-bit) every eighth clock cycle from code 0 to code 2047

101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern)

110 = Unused

111 = Unused

7 6 5 4 3 2 1 0

LVDS CLKOUT LVDS DATA

0 0 0 0 0 0

STRENGTH STRENGTH

Bits[7:2] Always write '0'

Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength

This bit determines the external termination to be used with the LVDS output clock buffer.

0 = 100Ω external termination (default strength)

1 = 50Ω external termination (2x strength)

Bit 0 LVDS DATA STRENGTH: LVDS data buffer strength

This bit determines the external termination to be used with all of the LVDS data buffers.

0 = 100Ω external termination (default strength)

1 = 50Ω external termination (2x strength)

Product Folder Link(s): ADS58B18 ADS58B19