Datasheet
t
SCLK
t
DSU
t
DH
t
SLOADS
t
SLOADH
SDATA
A7
A6 A5
A4 A1
A0
A2
A3
D7
D6 D5
D4 D1
D0
D2
D3
SCLK
SEN
RESET
RegisterAddress RegisterData
ADS58B18
ADS58B19
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SBAS487D – NOVEMBER 2009–REVISED JANUARY 2011
SERIAL INTERFACE
The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface
formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data)
pins. When SEN is low, the serial shift of bits into the device is enabled, the serial data (on SDATA) are latched
at every falling edge of SCLK, and the serial data are loaded into the register at every 16th SCLK falling edge.
In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in
multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the
remaining eight bits are the register data. The interface can work with SCLK frequency from 20MHz down to very
low speeds (a few hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through hardware reset by applying a high pulse on the RESET pin (of width greater than 10ns), as
shown in Figure 12; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high.
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In
this case, the RESET pin is held low.
Figure 12. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at +25°C, minimum and maximum values across the full temperature range: T
MIN
= –40°C to T
MAX
= +85°C,
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.
PARAMETER MIN TYP MAX UNIT
f
SCLK
SCLK frequency (equal to 1/t
SCLK
) > DC 20 MHz
t
SLOADS
SEN to SCLK setup time 25 ns
t
SLOADH
SCLK to SEN hold time 25 ns
t
DSU
SDATA setup time 25 ns
t
DH
SDATA hold time 25 ns
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