Datasheet

O
E
O
E
O
E
O
E
O
EE
O
E
O
E
O
E
O
E
O
N+1 N+2
InputClock
CLKOUTM
CLKOUTP
OutputData
(2)
(DXP,DXM)
DDRLVDS
N 1- N N+1
CLKOUT
OutputData
ParallelCMOS
InputSignal
SampleN
N+1
N+2
N+3 N+4
N+16
N+17
N+18
t
A
t
SU
t
SU
t
H
t
H
t
PDI
t
PDI
CLKP
CLKM
N 16- N 15- N 14- N 13-
N 16- N 15- N 14-
N 13-
N 12-
16ClockCycles
(1)
N
16ClockCycles
(1)
ADS58B18
ADS58B19
SBAS487D – NOVEMBER 2009– REVISED JANUARY 2011 www.ti.com
(1) At higher sampling frequencies, t
DPI
is greater than one clock cycle, which then makes the overall latency = ADC latency + 1.
(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).
Figure 8. Latency Diagram
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