Datasheet
ADS58B18
ADS58B19
SBAS487D – NOVEMBER 2009– REVISED JANUARY 2011
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TIMING REQUIREMENTS: LVDS and CMOS Modes
(1)
(continued)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock,
C
LOAD
= 5pF
(2)
, and R
LOAD
= 100Ω
(3)
, unless otherwise noted. Minimum and maximum values are across the full temperature
range: T
MIN
= –40°C to T
MAX
= +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER CONDITIONS MIN TYP MAX UNIT
DDR LVDS MODE (continued)
Duty cycle of differential clock, (CLKOUTP –
LVDS bit clock duty
CLKOUTM) 42 48 54 %
cycle
1MSPS ≤ sampling frequency ≤ 250MSPS
Rise time measured from –100mV to +100mV
Data rise time,
t
RISE
, t
FALL
Fall time measured from +100mV to –100mV 0.14 ns
Data fall time
1MSPS ≤ sampling frequency ≤ 250MSPS
Output clock rise Rise time measured from –100mV to +100mV
t
CLKRISE
,
time, Fall time measured from +100mV to –100mV 0.14 ns
t
CLKFALL
Output clock fall time 1MSPS ≤ sampling frequency ≤ 250MSPS
Output enable (OE) to
t
OE
Time to valid data after OE becomes active 50 100 ns
data delay
PARALLEL CMOS MODE
(8)
Input clock to data Input clock rising edge cross-over to start of data
t
START
1.1 ns
delay valid
(9)
t
DV
Data valid time Time interval of valid data
(9)
2.5 3.2 ns
Input clock rising edge cross-over to output clock
Clock propagation
t
PDI
rising edge cross-over 4 5.5 7 ns
delay
1MSPS ≤ sampling frequency ≤ 200MSPS
Output clock duty Duty cycle of output clock, CLKOUT
47 %
cycle 1MSPS ≤ sampling frequency ≤ 200MSPS
Rise time measured from 20% to 80% of DRVDD
Data rise time,
t
RISE
, t
FALL
Fall time measured from 80% to 20% of DRVDD 0.35 ns
Data fall time
1 ≤ sampling frequency ≤ 250MSPS
Output clock rise Rise time measured from 20% to 80% of DRVDD
t
CLKRISE
,
time, Fall time measured from 80% to 20% of DRVDD 0.35 ns
t
CLKFALL
Output clock fall time 1 ≤ sampling frequency ≤ 200MSPS
Output enable (OE) to
t
OE
Time to valid data after OE becomes active 20 40 ns
data delay
(8) For f
S
> 200MSPS, it is recommended to use an external clock for data capture instead of the device output clock signal (CLKOUT).
(9) Data valid refers to a logic high of 1.26V and a logic low of 0.54V.
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